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1 datasheet time of flight (tof) signal processing ic isl29501 the isl29501 is a time of flight (tof ) based signal processing integrated circuit. the sensor enables low cost, low power and long range optical distance se nsing when combined with an external emitter and detector. the isl29501 has a built-in curren t dac circuit that drives an external led or laser. the modulated light from the emitter is reflected off the target and is received by the photodiode. the photodiode then converts the returned signal into current, which is used by the isl29501 for signal processing. an on-chip digital signal processor (dsp) calculates the time of flight, which is proportional to the target distance. the isl29501 is equipped with an i 2 c interface for configuration and control. use of an external photodiode and emitter allows the user to optimize the system design for performance, power consumption and distance measur ement range that suit their industrial design. the isl29501 is wavelength agnostic and permits the use of other optical wavelengths if better suited for applications. features ? enables proximity detection and distance measurement ? modulation frequency of 4.5mhz ? emitter dac with programmable current up to 255ma ? operates in continuous and single shot mode ? on-chip active ambient light rejection ? auto gain control mechanism ? interrupt controller ? supply voltage range of 2.7v to 3.3v ?i 2 c interface supporting 1.8v and 3.3v bus ?low profile 24 ld 4x5 qfn package applications ? mobile consumer applications ? industrial proximity sensing ? power management ? home automation related literature ? ug054 , ?isl29501 evaluation software user guide? ? ug055 , ?ISL29501-ST-EV1Z sand tiger user guide? ? ug081 , ?isl29501-csevkit1z cat shark user guide? ? an1966 , ?isl29501 sand tiger optics application note? ? an1917 , ?isl29501 layout design guide? figure 1. application diagram ir led pd c 2 c 1 c 3 r 1 r 2 r 3 host mcu r 4 c 4 2.7v to 3.3v ss avss dvss dvcc pdp pdn avcc rset cen scl sda evcc eir evss irq vout a1 a2 avdd 2.7v to 3.3v 2.7v to 3.3v r 4 r 5 june 29, 2016 fn8681.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl29501 2 fn8681.3 june 29, 2016 submit document feedback table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 i 2 c electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 6 principles of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chip enable (cen) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sample start (ss) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 interrupt (irq) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 sampling modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 single shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 emitter driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 eir pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 main dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 threshold dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 connecting the photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . 10 selecting the photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 emitter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ambient light rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ambient adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 chip identification (address) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 a2 and a1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 system level calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 crosstalk calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 distance offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 optical system design considerations. . . . . . . . . . . . . . . . 16 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pcb design practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . 21 general power pad design considerations . . . . . . . . . . . . 21 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 about intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
isl29501 3 fn8681.3 june 29, 2016 submit document feedback pin configuration isl29501 (24 ld qfn) top view block diagram figure 2. block diagram digital calibration and processing a to d converter oscillator i 2 c sda scl pdp pdn emitter driver irq ss eir evss av bpf avcc dvdd evcc avss dvss rset - + pin descriptions pin # pin name description 1, 2, 13 avss tie to avss. 3 cen chip enable. active low. 4a2i 2 c address bit, pull to dvcc or dvss 5sdai 2 c data bus. 6scli 2 c clock bus. 7a1i 2 c id address bit, pull to dvcc or dvss. 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 avss avss cen a2 sda scl a1 avdd vout avcc avss dvss dvcc avss rset avss pdn pdp avss irq ss evss eir evcc epad pull-up to supply is required. 9 ss sample start: input signal with high to low edge active. 10 evss emitter driver ground. connects to cathode of emitter. 11 eir emitter driver output. connects to anode of emitter. 12 evcc emitter driver supply. decouple with 2.2f or larger capacitor along with a 0.1f for high frequency. 14 dvcc digital power 2.7v to 3.3v supply. 15 dvss digital power ground. 16 avss analog power ground. 17 avcc analog power 2.7 to 3.3v supply. 18 vout afe ldo output, tied to avdd, decouple with 1f and 0.01f capacitor pair. 19 avdd afe analog supply. 20, 23 avss analog ground shield. 21 pdp photodiode cathode input. 22 pdn photodiode anode input. 24 rset sets chip bias current. tie to 10k resistor 1% to avss ground. epad center epad: tied to avss. pin descriptions (continued) pin # pin name description
isl29501 4 fn8681.3 june 29, 2016 submit document feedback ordering information part number ( notes 1 , 2 , 3 ,) part marking v dd range (v) temp range (c) tape and reel (units) package (rohs compliant) pkg. dwg. # isl29501irz-t7 29501 irz 2.7v to 3.3v -40 to +85 1k 24 ld qfn l24.4x5f isl29501irz-t7a 29501 irz 2.7v to 3.3v -40 to +85 250 24 ld qfn l24.4x5f ISL29501-ST-EV1Z sand tiger evaluation board isl29501-cs-evkit1z cat shark evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl29501 . for more information on msl please see techbrief tb477 .
isl29501 5 fn8681.3 june 29, 2016 submit document feedback absolute maximum rating s thermal information supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 4v voltage on all other pins . . . . . . . . . . . . . . . . . . . . . . . . (-0.3v to v cc ) + 0.3v esd rating human body model (tested per jesd22-a114e) ( note 6 ) . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v latch-up (tested per jesd-78c; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) qfn package ( notes 4 , 5 ) . . . . . . . . . . . . . 35 1.2 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 3.3v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. esd hbm passed 2kv with exception to pins irq and sda, which passed 1kv. electrical specifications unless otherwise indicated, all the following tables are at dvcc, avcc and evcc at 3v, t a = +25c, boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 8 )typ max ( note 8 )unit sensor parameters modulation frequency f mod modulation frequency of emitter 4.45 4.5 4.65 mhz chip power supply dvcc, avcc, evcc 2.7 3.0 3.3 v delay from chip enable to first sample tcen_fs note 7 500 s delay between sleep mode to start of first sample tsleep_fs note 7 3 s quiescent current - sleep mode, dvcc+avcc+evcc i s-hs cen = 1; i 2 c disable; register values are retained; ss = sda = scl = v cc 2.5 a quiescent current - shutdown, dvcc+avcc+evcc i s-sd cen = 0; i 2 c enable; register values are retained; all other functions are disabled 1 a chip current while measuring, dvcc+avcc+evcc iddact emitter duty cycle = 50%, 0x90 = 06h, 0x91 = 00h 55 ma afe specifications maximum afe input current pdp/pdn imax_pd design recommendation 12.8 a voltage at pdp vpdp 1.7 v voltage at pdn vpdn 0.75 v low noise amplifier lna provides unity gain 1x n/a differential i to v conversion range tia gain 0x97[0:1], b0 = 0 and b1 = 0 default 8k k maximum photodiode capacitance recommended cmax design recommendation 15 pf
isl29501 6 fn8681.3 june 29, 2016 submit document feedback i 2 c electrical specifications for scl, sda, a1, a2, irq unless otherwise stated, v dd = 3v, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 8 ) typ ( note 9 ) max ( note 8 )unit supply voltage range for i 2 c specification v i2c 1.8 3.3 v input leakage i il v in = gnd to v cc 1 a input low voltage v il -0.3 0.3 x v cc v input high voltage v ih 0.7 x v cc v cc + 0.3 v sda and scl input buffer hysteresis vhys 0.05 x v cc v sda output buffer low voltage v ol i ol = 3ma 00.4 v pin capacitance ( note 10 )c pin 10 pf scl frequency f scl 400 khz pulse width suppression time at sda and scl inputs t sp any pulse narrower than the maximum specification is suppressed 50 ns scl falling edge to sda output data valid t aa scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns time the bus must be free before the start of a new transmission t buf sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns clock low time t low measured at the 30% of v cc crossing 1300 ns clock high time t high measured at the 70% of v cc crossing 600 ns start condition set-up time t su:sta scl rising edge to sda falling edge; both crossing 70% of v cc 600 ns start condition hold time t hd:sta from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns input data set-up time t su:dat from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns input data hold time t hd:dat from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0 ns stop condition set-up time t su:sto from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns stop condition hold time for read, or volatile only write t hd:sto from sda rising edge to scl falling edge; both crossing 70% of v cc 1300 ns output data hold time t dh from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0 ns sda and scl rise time t r from 30% to 70% of v cc 20 + 0.1 x cb 250 ns sda and scl fall time t f from 70% to 30% of v cc 20 + 0.1 x cb 250 ns capacitive loading of sda or scl cb total on-chip and off-chip 10 400 pf sda and scl bus pull-up resistor off-chip rpu maximum is determined by t r and t f for cb = 400pf, maximum is about 2k ~2.5k for cb = 40pf, maximum is about 15k ~ 20k 1 k output leakage current (sda only) i lo v out = gnd to v cc 1 a a1, a2, sda and scl input buffer low voltage v il -0.3 v cc x 0.3 v
isl29501 7 fn8681.3 june 29, 2016 submit document feedback a1, a2, sda and scl input buffer high voltage v ih v cc x 0.7 v cc v sda output buffer low voltage v ol 00.4 v capacitive loading of sda or scl c l 10 400 pf notes: 7. product characterization data. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. typical values are for t a = +25c and v cc = 3.3v. 10. cb = total capacitance of one bus line in pf. i 2 c electrical specifications for scl, sda, a1, a2, irq unless otherwise stated, v dd = 3v, t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 8 ) typ ( note 9 ) max ( note 8 )unit
isl29501 8 fn8681.3 june 29, 2016 submit document feedback principles of operation the isl29501 operates using the principle of square wave modulated indirect time of flight (swm-itof). the sensor operates in frequency domain an d takes advantage of the analog signal processing techniques to obtain distance measurements from phase shift. the isl29501 ic partnered with an external emitter and detector, functions as a distance and ranging sensor. the chip emitter driver transmits a modulated square wave (tx) at a given frequency optical signal (f mod ) through the emitter, the received optical signal (rx) returns with phase shift and attenuation dependent on object distance and reflectivity (see figure 3 ). the phase difference between em itted and received signals of the modulated square wave is determined in frequency domain and is converted to a distance measurement. the distance is computed using an internal dsp with the results provided to the host through an i 2 c interface. the phase shift of the return sign al is dependent on the distance of the object from the system and is relatively independent to the object reflectivity. the distance of the object can be calculated by determining the phase shift of the return signal using equation 1 . where: d is the distance of the object from the sensor system. f mod is the modulation frequency. is the phase difference betw een emitted and returns signal. c is the speed of light. key constants can be derived from this expression for f mod = 4.5mhz (the system frequency) whose values can be useful in developing a general understanding of the system. ?5.3m/radian ? 33.3m for cycle (2 radians) ? 15cm/ns delay the range of the system can be optimized for each application by selecting different components (emitter, detector) and optics. the sensor takes advantage of analog quadrature signal processing techniques to obtain the phase difference between the emitted and received signals. some of the processing steps in the signal chain are listed in the following paragraph. the afe (analog front end) converts the photocurrent into a voltage, which it does in 2 stages. the first stage is a transimpedance amplif ier (tia), which converts the photodiode current into voltage. the second stage is a low noise amplifer (lna) that buffers this voltage for rest of the analog signal chain. the demodulator translates this signal into i (in phase) and q (quadrature) components. i and q values are filtered and the digitized by the adc. the dsp calculates the distance based on the amplitude, phase and frequency values. figure 3. transmitted and received signal in a system isl29501 tx 2 ? f m t ?? sin = rx r 2 ? f m t ? C ?? sin = d c 4 ? f mod ------------------------------ ?? = (eq. 1) ?? adc lpf adc lpf i q 0 90 v in
isl29501 9 fn8681.3 june 29, 2016 submit document feedback the afe in conjunction with the gain from the agc loop allows for selection of different detectors in application design. the adc relies on the automatic gain control loop to evaluate the optimal setting for data conversion. this prevents saturation when the target is at short range. functional overview the following paragraphs provide additional detail to the function of the important blocks in the isl29501. a dditional in formation may be available in the related literature on page 1 . power supply pins the isl29501 will operate with a voltage range from 2.7v to 3.3v. there are three power rails: avcc, dvcc and evcc. the avcc and dvcc supply the digital and analog part of circuits while the evcc is dedicated to the emitter driver section. intersil recommends decoupling the analog and digital supplies to minimize supply noise. noise can be random or deterministic in nature. random noise is decoupled like in any other system. synchronous noise (4.5mhz) is seen as crosstalk by the chip and directly affects distance meas urements. crosstalk calibration will mitigate this but it is better to target this frequency directly, particularly on evcc. power-on reset when power is first applied to the dvcc pin, the isl29501 generates an internal reset. the re set forces all registers to their default values and sets the sequencer to an initial state. chip enable (cen) pin the cen pin is an active low input pin. when asserted (pulled low), the device will bias the internal circuit blocks, band gaps, references and i 2 c interface. once cen is enabled writing 0x01 b0 = ?1? will disable the chip. it can be re-enabled by writing it back to ?0? providing cen stays low. this allows software control. register 0x01 defaults to 0 or enabled. changing chip enable does not alter register values. sample start (ss) pin sample start (ss) pin is an input logic signal, which triggers a measurement cycle. this signal is needed to start measurements in free run mode and for each measurement in single shot mode. if a trigger is received during an active measurement the request is ignored. command register the command register (0xb0) allows the user to operate under software control. there are 3 commands that each perform useful functions withou t hardware interaction. ? a soft-start can be initiated by writing 0xb0 to 0x49. this register bit emulates the single shot pin. this acts like the ss pin to start measurements. ? a soft-reset can be initiated by writing 0xb0 to 0xd7. this action resets all registers to po wer-on default values with the exception of brownout bit. this function performs similar to the power cycle. ? a soft-clear can be initiated by writing to 0xb0 to 0xd1, this stops all conversions and resets the accumulators and the sensor will stop if it is in cont inuous mode. this function is a sequencer reset. interrupt (irq) pin the isl29501 can be configured to generate interrupts at the completion of a sensing cycle. th is allows the host to perform other tasks while a measurement is running. the irq pin is an active low output logic pin. it is an open-drain output pin and requires a pull-up resistor to dvcc. the host should service the irq request by reading the 0x60 register. the register is cleared upon reading (self clear). if the sensor is set to signal sample mode, then the sensing stops and awaits for the next sample start signal. if the isl29501 is set to continuo us mode, then th e ic will begin the next sensing sample according to the preconfigured sampling time period. sampling modes the isl29501 provides two operatin g sample modes; single shot mode and continuous mode. single shot in single shot mode one measurement is made. the sampling period is normally not important since the mcu is controlling each measurement. the duration of the measurement is controlled by the integration time and the mcu latency. this allows the greatest flexibility of the measurement duty cycle and therefore the power consumption. continuous mode continuous mode operation is used for systems where the sensor is continuously gathering data at a predefined integration and sampling period using the internal timing controller. this is the chip default. the data is available to the host after every sample period and the sensor will keep operating in this mode until changed by the mcu. if the interrupt is enabled the irq pin will toggle after each measurement. by adjusting the sample period and the sample period range (registers 0x11 and 0x12) over 3.5 seconds between measurements is possible. for measurement intervals greater than this single shot mode must be used. table 1. reg0x13 sampling modes register bit preference mode of operation 0x13[0] 0 continuous sampling 0x13[0] 1 single shot sampling
isl29501 10 fn8681.3 june 29, 2016 submit document feedback emitter driver integrated in the isl29501 is an emitter driver circuit. it is a current source designed to drive either the ir led or laser. the circuit is enhanced to provide fast turn-on and turn-off of either led or lasers. the driver needs ab out 1v of headroom to operate properly. it will still operate with lower voltages but the driver becomes less linear the lower you go. headroom is defined as the voltage across the driver evdd - v forward emitter . this may limit the optical power of certain lasers. eir pin figure 5 shows a simplified block diagram of the emitter driver. the circuit consists of two primary current dacs, main and threshold dac. the eir pin is connected to the emitter anode while the cathode is tied to ground (evss). the drive current is derived from a combination of a range (0x90) and value (0x91) dacs allowing a wide range of values. main dac the main dac is implemented in two separate dacs. combined they are designed to output a maximum current of 255ma of switched (pulsed) current. the current value is set by programming registers 0x90 and 0x91. register 0x90 is the range control and register 0x91 for fine control. depending on the application?s desired range and the type of emitter employed, the current level can be set to give the best snr performance. the system desi gner will have to determine this value based on component sele ction. in addition, this fine tuning allows the ap plication to compensate for production variation in the external components. the emitter current is governed by the following formula: irdr = 0x90[3:0]/15*0x91[7:0]/255*255ma threshold dac in addition to the main dac there is a threshold dac that can provide dc current to the emitter. this might be useful in some laser applications by raising the off current to just below its threshold. the threshold current is active only during integration time to limit power consumption. threshold current is not needed in most applications. a maximum of 30ma can be driven by the threshold dac. the current is programmed in register 0x93. the detailed description can be found in the ? register map ? on page 17 . connecting the photodiode the photodiode should be connected between the pdn and pdp pins as shown in figure 7 . the photodiode operates in photoconductive mode, the voltages at pdp and pdn nodes are listed in the afe specifications . the photodiode is reversed biased with anode at 0.7v and the cathode at 1.7v (1v reverse bias). biasing the diode in photoconductive mode enables lower effective capacitance/faster operat ion and efficient collection of photo energy. selecting the photodiode this section provides general guidelines for the selection of the photodiode for receiver. three key parameters that must be considered: 1. peak wavelength 2. collected light 3. rise/fall time a detector with narrow band sensitivity in the nir or mwir are best for proximity sensing as most ambient light will be naturally rejected. the ideal pd would be a narrow band pass that is centered on the emitter peak wavelength. diodes with no filter offer poor performance and should not be considered. we have to ensure that the emitter peak wavelength is aligned with the detector wavelength to achieve high snr. maximizing the collected light can be achieved with the largest active area the mechanical cons traints allow or through the use figure 5. emitter connectivity 0x90[0:3] 0x91[0:7] evcc eir evss figure 6. typical emitter waveform and features figure 7. connecting pd to afe irdr(ma) threshold dc 4.5mhz square wave amplitude time (s) pdn pdp vbp = 0.7v vbn = 1.7v dc correction avss avdd gain + + - -
isl29501 11 fn8681.3 june 29, 2016 submit document feedback of a lens. pds in a traditional led package have a built in lens so the effective active area can be 20 times more the silicon area would suggest. large area diodes are accomp anied with larger intrinsic capacitances leading to slow rise and fall times. there is a trade off between detector area and capacitance that need to be considered for system performance. the fully differential front-end converts the photo current into voltage and allows for common-mode noise/crosstalk to be rejected. an effective capacitance of less than 15pf is recommended for robust performance, for applications where distance measurement is required. using larger capacitance will cause increase in noise and not functional failure. the decision to use small or large photodiode (i.e., capacitance) has to be made by the system engineer based on the application. emitter selection the isl29501 supports the use of light sources such as leds, vcsels and lasers. the sensor will drive any emitter within the maximum current range supported by the emitter dac. the sensor working principle is wavelength agnostic and determination of wavelength can be made based on application. the emitter wavelength should be an nir or mwir (i.e., 800nm to 1300nm) to minimize the infl uence of ambient light on the precision. the selection between an led or laser depends on the user application. some general system considerations are distance, field of view and precision requirements. while an led is a reliable light source, it might no t be the best suited for long distance due to its dispersion char acteristics. however, it is good for short range and large area coverage. for higher optical power lasers/vcsel may offer an advantage. lasers are more efficient but are more complicated to implement due to eye safety requirements and higher forward voltages. ambient light rejection ambient light results in a dc current in the tia. a feedback loop supplies negates this current to prevent impact to the signal path. subsequent st ages of the analog signal chain are ac coupled and are not susceptible to dc shifts at afe. ambient light will alter the photon to current delay in the photodiode. this is not an issue if the ambient light is constant but if it changes, the delay in the photodiode changes, which could result in distance error. to minimize the effect of am bient on the system distance measurements, the sensor enables correction algorithms (linear and second order polynomial to correct for any diode related behaviors). once coefficients are determined and programmed, the ambient induced delay (distance error) is subtracted real time in the chip dsp. ambient current value can be found by reading register 0xe3. power consumption in a ?time of flight? application power consumption has two components; the power consumed within the isl29501 device and the power consumed by the emitter led or vscel. while the emitter current is load current and not part of the isl29501 power dissipation, it is included in this discussion to help the user understand the entire ?time of fl ight? contribution to the total application power budget (see equation 2 ). ic power consumption the power consumed in the isl29501 has two components. the first is the standby current, which is present whenever the chip is not integrating (making a meas urement). the second is the current consumed during a measurement. chip current is calculated by multiplying the overall duty cycle by 102ma and adding the standby current (~2m a). the overall duty cycle is defined as (integration time/sam pling period/2) in continuous mode or the (integration time /user measurement repetition rate/2) in single sample mode see equation 3 . typical values for i standby can be found in the "electrical specification table" on page 5 . total time of flight power consumption to calculate the total ?time of flight? module current, the load current contribution must be added to the chip current. as with the chip current, the measurement duty cycle has a large effect on the load current. the load curre nt is defined as the product of the emitter current and the overall measurement duty cycle (see equation 4 ). the emitter current is calculated using equation 5 : the duty cycle for this calculation is the same as described in the ic power consumption section. in the application, the best emitter current setting is a balanc e of the required optical power and the acceptable power consumption. similarly, the duty cycle is a balance between the precision of a measurement and power consumption. it should be noted that choosing high duty cycles can cause heating of the emitter introducing drift in distance measurements. for additional details refer to ? emitter selection ? on page 11 and ? integration time ? on page 12 . shutdown shutdown disables all the indivi dual components that actively consume power, with the exception of the i 2 c interface. there are multiple options for the system designer based on the time to bring up the system. idd tof idd ic idd load + = (eq. 2) idd ic 102ma dc overall ? i s dby tan + = (eq. 3) load i dc overall i emitter ? = (eq. 4) i emitter reg0x90 15 ? ? reg0x91 255 ? ? ? ? 255ma ? ? = (eq. 5)
isl29501 12 fn8681.3 june 29, 2016 submit document feedback the cen (chip enable), in conjunction with shutdown, can be used to keep the system passive based on power consumption and speed of response. sampling time the sampling waveform in figure 8 on page 13 dictates the sensor operation. the key elements to understand are integration time and sampling interval. integration time dictates the driv er waveform active period and sampling frequency provides the da ta output rate of the sensor. optimal values for integration time and sampling interval (duty cycle) determine the power consumption and performance of the system (precision). a typical emitter driver waveform is shown in figure 9 on page 13 to indicate the controls that are available to the user. sampling interval determines the se nsor response time or rate of output from the sensor, this is user-defined with equation 6 : the value for sampling frequency ranges from 1ms to 1843ms. for a more detailed description of the register please refer to the ? register map ? on page 17 . the ratio of integration time to sampling frequency is the sensor duty cycle. duty cycle determines the power consumption of the sensor. when building an optical system, a determination of an effective duty cycle will help optimize power and performance trade-offs in the system. integration time integration time sets the emitte r dac active time. the value is user controlled by the register interface. if the sample integration time is set to be greater than the sample period, then the integration time will default to maximum allowable within the sample period. integration time impacts precis ion and power consumption of the chip and can be used as a measure to optimize the system performance. for more detailed description of register please refer to the ? register map ? on page 17 . automatic gain control the isl29501 has an advanced automatic gain control loop, which sets the analog signal le vels at an optimum level by controlling programmable gain amplifiers. the internal algorithms determine the criteria for optimal gain. the goal of the agc controller is to achieve the best snr response for the given application. ambient adc the ambient adc measures the level of ambient light present in the environment. while this does not directly effect isl29501 operation it can make changes in the photodiode that will effect distance measurements. an a ccurate measurement scheme makes real time correction in changing ambient light possible. the ambient adc operation does not interfere with sensor operation. the ambient light magnitude can be read from register 0xe3[7:0]. this register tracks the ambient photocurrent. the ambient photocurrent values can be used to estimate the best achievable snr/precis ion performance for a given environment. sampling frequency 450 ? s 1 sample_period[7:0] + 2 sample_skip[3:0] ? ?? ? (eq. 6) (eq. 7) integration time 71.1 ? s2 sample_len[3:0] ? = maximum integration time 71.1 ? s2 11 ? (145.6ms) =
isl29501 13 fn8681.3 june 29, 2016 submit document feedback figure 8. waveform for functional operation figure 9. emitter driver wave form ? sampling time integration tim e analog on led driver on i and q computation on analog on led driver on i and q computation on continuous mode irdr (ma) dc prebias leve l integration time 4.5mhz square wave amplitude sampling time time (s) figure 10. automatic gain control agc controller pdp pdn bpf adc + -
isl29501 14 fn8681.3 june 29, 2016 submit document feedback data outputs the sensor outputs a wide variet y of information that can be used by the mcu for processing. a list of parameters that can be obtained from the sensor are identified in the following. the information can be relied upon by the digital logic to generate interrupts for quick decision making or used for other off-chip processing functions. ? distance information ? magnitude information ?raw i and q values ?chip junction temperature ? emitter forward voltage ? interrupts for proximity and presence detection ? enable motion computation base d on time stamped distance values the validity of data can be used to screen interrupts based on user requirements enabling robu st use cases. details for these registers are contained in table 3 on page 20 . interrupt controller the interrupt controller is a useful block in the digi tal core of the isl29501. the interrupt controller generates interrupts based on sensor state. this allows the user to free up the mcu to do other tasks while measurements are in progress. noise rejection electrical ac power worldwide is distributed at either 50hz or 60hz and may interfere with sensor operation. the isl29501 sensor operation compensated fo r this and rejects these noise sources. i 2 c serial interface the isl29501 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the mast er and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl29501 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. this device supports multibyte reads. chip identification (address) the isl29501 has an i 2 c base address of 0xa4. a2 and a1 pins a2 and a1 are address select pins and can be used to select one of 4 valid chip addresses. a2 and a1 must be set to their correct logic levels, see i 2 c electrical specifications on page 6 for details. the lsb chip address is the read/write bit. the value is ?1? for a read operation, and ?0? for a write operation (see table 2 ). a1 and a2 should be tied to dvss for default operation. protocol conventions data states on the sda line can change only during scl low periods. the sda state changes du ring scl high are reserved for indicating start and stop conditions (see figure 11 on page 15 ). on power-up of the isl29501, the sda pin is in the input mode. all i 2 c interface operations must be gin with a start condition, which is a high to low transition of sda while scl is high. the isl29501 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 11 ). a start condition is ignored during the powe r-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 11 ). a stop condition at the end of a read operation, or at the end of a writ e operation places the device in its standby mode. an ack (acknowledge), is a software convention used to indicate a successful data transfer. the tr ansmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 12 on page 15 ). the isl29501 responds with an ack after recognition of a start condition followed by a valid identification (a.k.a. i 2 c address) byte. the isl29501 also responds with an ack after receiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, a data byte and a stop condition. after each of the three bytes, the isl29501 responds with an ack. stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ack signal. if a stop by te is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the isl29501 resets itse lf without performing the write. read operation a read operation is shown in figure 14 on page 15 . it consists of a minimum 4 bytes: a start followed by the id byte from the master with the r/w bit set to 0, then an ack followed by a register address byte. the master terminates the read operation by not responding with an ack and then issuing a stop condition. this operation is useful if the master knows the current address and desires to read one or more data bytes. table 2. identification byte format 10101a2a10 (msb) (lsb)
isl29501 15 fn8681.3 june 29, 2016 submit document feedback a random address read operation consists of a two-byte ?write? instruction followed by a register read operation (see figure 14 ). the master performs the following sequence: a start, a chip identification byte with the r/w bit set to ?0?, a register address byte, a second start and a second chip identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl29501 responds with an ack. while the master continues to issue the scl clock, isl29501 will transmit data bytes as long as the master responds with an ack with the 9th clock. the register address will automatically increment by 1 after ack so the next register?s data will come out with succeeding scl clocks. the master terminates the read operation by issuing a stop condition following the last bit of the last data byte (see figure 14 ). figure 14. multibyte read sequence start data data stop stable change data stable figure 11. valid data change s, start and stop conditions scl sda sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 12. acknowledge response from receiver s t a r t s t o p chip address byte with r/w = 0 reg address byte data byte a c k signals from the master signals from the isl29501 a c k 1 0 1 00 a c k write signal at sda 000 0 a1 a2 100 figure 13. example byte write sequence 0 0 1 0 0 0 0 0 0 1 signals from the master signals from the slave signal at sda s t a r t chip address byte with r/w = 0 reg address byte a c k a c k 10 1 00 s t o p a c k 11 1 00 chip address byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 1a2a1 1 110 00 1a2a1 00 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6d5d4d3d2d1d0
isl29501 16 fn8681.3 june 29, 2016 submit document feedback system level calibration the goal of calibration on the isl29501 is to be able to calibrate the sensor performance for different external components that are paired with the sensor and ensure stable operation across supply range and temperature. there is no nonvolatile memory on-chip and the user will have to use the i 2 c to program the register values during initialization. crosstalk calibration crosstalk is defined as signal that reaches the isl29501 chip directly without bouncing of the ta rget. this can be electrical or optical. at close range a large return signal values crosstalk has a minor impact on distance meas urements. at the far end of the distance range, the crosstalk mi ght exceed the signal adding error to measurements. the isl2950 1 has the ability to do a real time subtraction of crosstalk from the returned signal resulting in a more accurate measurement. if the crosstalk remains constant, this subtraction is very effective. this is normally a one-time calibration performed at the factory in controlled conditions. for this calibration, the user makes a distance measurement with the return signal blocked from reaching the photodiode. since the chip sees none of the emitted signal anything received is crosstalk. with little to no signal, gaussian noise will dominate these measurements. to elimin ate this noise the crosstalk measurement needs to be averaged. the averaged value is then written into the chip where it will be subtracted real time from all succeeding distance measurements. a detailed description of registers is provided in the ? register map ? on page 17 , registers 0x24 to 0x2b hold the crosstalk calibration values. if these registers remain at default values (0x00) no correction will occur. distance offset calibration variation in delay of emitter type s, photodiodes and circuit board design will change the signal path delay. to compensate for this, a reference point at a known dist ance needs to be established. this reference is calculated during distance calibration. the process involves making a dist ance measurement at a known distance, subtracting that distan ce from a raw measurement and writing the difference into the distance calibration registers 0x2f/0x30. once these calibration registers are written all succeeding distance will have this value subtracted real time from the measured value. to insure the correct value is subtracted an average of several measurements needs to be done. depending on the emitter and photodiode choice this calibration should be required once per family (emitter/photodiode/board) type. optical system design considerations a system designed with the isl 29501 requires that emitter and detector are optically isolated for better performance. there needs to be a physical barrier or isolation between the emitter and detector to minimize direct optical signal coupling between emitter and detector. if a glass or other material is placed above the emitter detector, light from the led can reflect off the glass and enter the sensor. this can limit the range of the proximity measurement and manifests as faint objects in measurements. careful attention must be paid to some of the following design parameters: ? spacing between emitter and detector ? optical isolation between emitter and detector ? distance of the pcb from glass or from optical co-package the isl29501 architecture rejects most ambient optical interference signals that are lower or higher than the modulation frequency. a review of the ambient sources in the system will help you understand the amou nt of ambient light and the impacts on the precision measurements. emitter detector glass baffle pcb figure 15. simplified optical system
isl29501 17 fn8681.3 june 29, 2016 submit document feedback register map addr register name access default bit(s) bit name function comment page 0: control, settin g and status registers 0x00 device id ro 0xa 7:0 chip_id[7:0] device id default to '0a' 0x01 master control rw 0x00 0 c_en chip enable same meaning as cen pin 0: enabled (default) 1: disabled 0x02 status registers ro 0 enout ?1? = output enabled 1 ready ?1? = chip ready 2 vdd ok ?1? = internal power-good internal regular output voltage section 0.1: sampling control registers 0x10 integration period rw 0x02 2 3:0 sample_len[3:0] ? 71.1s*2 {sample_len[3:0]} maximum = 71.1s*2 11 =145.6ms controls the length of for each sample, which is equal to the time during, which the optical pulse is active. sample_len is also called integration time. this value dictates the number of pulses of the 4.5mhz clock on the eir pin. 0x11 sample period rw 0x00 7:0 sample_period[7 :0] controls the time between the start of each sample sample period = 450s*( sample_period[7:0]+1) 0x12 sample period range rw 0x00 1:0 sample_skip[1:0] sample skipping select 0: sample period multiplied by 2 0 1: sample period multiplied by 2 1 2: sample period multiplied by 2 2 3: sample period multiplied by 2 3 (default) 0x13 sample control rw 0x7c 0 0 adc_mode single-shot/free running 0: free ru nning, a single trigger to start is required 1: single shot, will only sample off external trigger 0 1 cali_mode calibration vs light order for single shot mode 0: calibration happens before light samples for single shot mode 1: calibration happens after light samples for single shot mode 3 3:2 cali_freq[1:0] sets frequency of calibration samples for free running mode 0: calibration sample after every 16 light samples 1: calibration sample after every 32 light samples 2: calibration sample after every 64 light samples 3: calibration sample after every 128 light samples 1 4 light_en light sample enable 0: calibration disabled 1: calibration enabled
isl29501 18 fn8681.3 june 29, 2016 submit document feedback 0x19 agc control rw 0x22 2 min_vga1_exp[2:0] set vga1 minimum set minimum allowed value of vga1 4 min_vga2_exp[2:0] set vga2 minimum set minimum allowed value of vga2 section 0.4a: closed loop calibration registers 0x24 crosstalk i exponent rw 0x00 7:0 i_xtalk_exp[7:0] crosstalk i ch annel exponent unsigned 8-bit exponent 0x25 crosstalk i msb rw 0x00 7:0 i_xtalk[15:8] cros stalk i channel msb signed 16-bit mantissa 0x26 crosstalk i lsb rw 0x00 7:0 i_xtalk[7:0] crosstalk i channel lsb 0x27 crosstalk q exponent rw 0x00 7:0 q_xtalk_exp[15:8] crosstalk q ch annel exponent unsigned 8-bit exponent 0x28 crosstalk q msb rw 0x00 7:0 q_xtalk[15:8] cros stalk q channel msb signed 16-bit mantissa 0x29 crosstalk q lsb rw 0x00 7:0 q_xtalk[7:0] crosstalk q channel lsb 0x2a crosstalk gain msb rw 0xff 7:0 gain_xtalk[15:8] crosstalk gain msb unsigned 16-bit integer 0x2b crosstalk gain lsb rw 0x00 7:0 gain_xtalk[7:0] crosstalk gain lsb 0x2c magnitude reference exp rw 0x00 3:0 mag_ref_exp[3:0] magnitude reference exponent unsigned 4-bit exponent 0x2d magnitude reference msb rw 0x00 7:0 mag_ref[15:8] magnitude reference significant unsigned 16-bit integer 0x2e magnitude reference lsb rw 0x01 7:0 mag_ref[7:0] 0x2f phase offset msb rw 0x00 7:0 phase_offset[15:8] fixed distance offset calibration msb unsigned 16-bit integer 0x30 phase offset lsb rw 0x00 7:0 phase_offset[7:0] fixed distance offset calibration lsb section 0.4b: ambient light and temperature corrections 0x31 temperature reference rw 0x00 7:0 ol_temp_ref[7:0] temperature reference reference for temperature correction 0x33 phase exponent rw 0x00 3:0 ol_phase_co _exp[3:0]? correction exponent unsigned 4-bit exponent for all corrections 0x34 phase temperature b rw 0x00 7:0 ol_phase_temp_b[7:0] temperature correction coefficient b equation format ax 2 +bx+c 0x36 phase ambient b rw 0x00 7:0 ol_phase_amb_b[7:0] amb ient correction coefficient b equation format ax 2 +bx+c 0x39 phase temperature a rw 0x00 7:0 ol_phase_temp_a[7:0] temperature correction coefficient a equation format ax 2 +bx+c 0x3b phase ambient a rw 0x00 7:0 ol_phase_amb_a[7:0] amb ient correction coefficient a equation format ax 2 +bx+c register map (continued) addr register name access default bit(s) bit name function comment
isl29501 19 fn8681.3 june 29, 2016 submit document feedback section 0.4: interrupt registers 0x60 interrupt control rw 0x00 2:0 interrupt_ctrl[2:0] select which interrupt mode to be used. 0: interrupts disabled 1: data ready 3: interrupts disabled section 0.7: analog control registers 0x90 driver range rw 0x06 3:0 driver_s[3:0] current dac scale sets the maximum emitter driver 4.5mhz current (i.e., the peak of the square wave) 0x91 emitter dac rw 0xfa 7:0 emitter_current[7:0] current dac value emi tter current calculation: peak current = (0x90[3:0])*emitter_current[7:0]/255 0x92 driver control rw 0x00 0 driver_thresh_en enable threshol d dac 0 - threshold dac disabled 1 - threshold dac enabled 0x93 threshold dac rw 0x00 7:0 driver_t[7:0 ] dc current added to signal current (register 0x90 & 0x91) double write required to update all bits in this register. 0xa5 emitter offset rw 3:0 emitter voltage meas offset lsb ? 0.125v, scales adc range for 0xe1 measurement 0xb0 command register rw 0x10 specific codes defined soft_start emulates sample start pin write 0xb0 = 0x49 soft_reset resets all registers write 0xb0 = 0xd7 soft_clear resets internal state machine write 0xb0 = 0xd1 register map (continued) addr register name access default bit(s) bit name function comment
isl29501 20 fn8681.3 june 29, 2016 submit document feedback data output registers table 3. data output registers and bit definitions addr register name access bit(s) bit name function comment 0xd1 distance readout msb rl 7:0 distance[15:8] distance output 16-bit integer, lsb = 1mm 0xd2 distance readout lsb rl 7:0 distance[7:0] distance output 0xd3 precision msb rl 7:0 precision[15:8] measurement noise approximation unsigned 16-bit integer 0xd4 precision lsb rl 7:0 precision[7:0] measurement noise approximation 0xd5 magnitude exponent rl 3:0 mag_exp[3:0] return signal magnitude unsigned 4-bit exponent 0xd6 magnitude significand msb rl 7:0 mag[15:8] return sign al magnitude msb unsigned 16-bit integer, lsb = 10fa 0xd7 magnitude significand lsb rl 7:0 mag[7:0] return signal magnitude lsb 0xd8 phase readout msb rl 7:0 phase[15:8] phase output msb unsigned 16-bit integer, /2pi for radians 0xd9 phase readout lsb rl 7:0 phase[7:0] phase output lsb 0xda i raw exponent rl 7:0 i_raw_exp[7:0] in phase exponent unsigned 8-bit exponent 0xdb i raw msb rl 7:0 i_raw[15:8] in phase msb unsigned 16-bit integer 0xdc i raw lsb rl 7:0 i_raw[7:0] in phase lsb 0xdd q raw exponent rl 7:0 q_raw_exp[7:0] quadrat ure phase exponent unsigned 8-bit exponent 0xde q raw msb rl 7:0 q_raw[15:8] quadrature phase msb unsigned 16-bit integer 0xdf q raw lsb rl 7:0 q_raw[7:0] quadrature phase lsb 0xe1 emitter voltage after rl 7:0 ev_after[7:0] emitter voltage unsigned 8-bit integer, lsb ~1.5mv 0xe2 die temperature rl 7:0 temperature[7:0] die temperature sensor measurement unsigned 8-bit integer, lsb ~1.15c 0xe3 ambient light rl 7:0 ambient[7:0] ambient light measurement unsigned 8-bit integer, lsb ~3.5a 0xe4 vga1 rl 7:0 vga1_setting[7:0] vga1 prog rammed setting unsigned 8-bit integer 0xe5 vga2 rl 7:0 vga2_setting[7:0] vga2 prog rammed setting unsigned 8-bit integer 0xe6 gain msb rl 7:0 gain_msb[15:8] agc gain msb unsigned 16-bit integer 0xe7 gain lsb rl 7:0 gain_lsb[7:0] agc gain lsb
isl29501 21 fn8681.3 june 29, 2016 submit document feedback pcb design practices ? the use of low inductance comp onents such as chip resistors and chip capacitors is strongly recommended. ? minimize signal trace lengths. trace inductance and capacitance can easily limit circuit performance. avoid sharp corners, use rounded corners when possible. vias in the signal lines add inductance at high frequency and should be avoided. this product is sensitive to noise and crosstalk. precision analog layout practices can be applied to this chip as well. ? pcb traces greater than 1" begi n to exhibit transmission line characteristics with signal rise/f all times of 1ns or less. high frequency performance may be degraded for traces greater than one inch, unless strip line is used. ? match channel-to-channel analog i/o trace lengths and layout symmetry. this will minimize propagation delay mismatches. ? maximize the use of ac decoupled pcb layers. all signal i/o lines should be routed over continuous ground planes (i.e., no split planes or pcb gaps under these lines). place vias in the signal i/o lines. ? use proper value and location of termination resistors. termination resistors should be as close to the device as possible. ? when testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. ? a minimum of two power supply decoupling capacitors are recommended (1000pf, 0.01f) and place as close to the devices as possible. do not use vias between the capacitor and the device because vias add unwanted inductance. larger capacitors can be farther away from the device. when vias are required in a layout, they should be routed as far away from the device as possible. pcb layout considerations the use of multilayer pcb stack up is recommended to separate analog and emitter supplies. placing a power supply plane located adjacent to the ground plane creates a large capacitance with little or no inductance. this will minimize ground bounce and improve power supply noise. the dielectric thickness separating these layers should be as thin as possible to minimize capacitive coupling. it is important that power supplies be bypassed over a wide range of frequencies. a combin ation of large and small width capacitors that self resonate around the modulation frequency will provide ample suppression of fundamental and harmonics that can be coupled to the sensor power supplies (check esr ratings). ensure that photodiode inputs pins (pdp and pdn) have symmetric and short traces and minimize placing aggressors around these routes, the guard shields provided on the ic should help minimize interference. ensure that emitter power (evcc and evss) and ground traces are low resistance paths with a short return path to emitter ground. minimize trace length and vias to minimize inductance and minimize noise rejection. the qfn package requires additional pcb layout rules for the thermal pad the thermal pad is electrically co nnected to v- supply through the high resistance ic substrate. it s primary function is to provide heatsinking for the ic. however, because of the connection to the v1- and v2- supply pins through the substrate, the thermal pad must be tied to the v- supply to prevent unwanted current flow to the thermal pad. maximum ac performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multilayered pc board. in cases where a dedicated layer is not possible, ac performance may be reduced at upper frequencies. the thermal pad requirements are proportional to power dissipation and ambient temperature. a dedicated layer eliminates the need for indivi dual thermal pad area. when a dedicated layer is not possible, an isolated thermal pad on another layer should be used. pad area requirements should be evaluated on a case-by-case basis. for additional information on pcb layout information see ? an1917 , ?isl29501 layout design guide? ? general power pad design considerations the following is an example of how to use vias to remove heat from the ic. we recommend that you fill the thermal pad area with vias. a typical via array would be to fill the thermal pad footprint spaced such that they are center -on-center 3x the radius apart from each other. keep the vias sm all, but not so small that their inside diameter prevents solder wicking through the holes during reflow. connect all vias to the potential outlined in the datasheet for the pad, typically the ground plane but not always, so check the pin description. it is impo rtant the vias have a low thermal resistance for efficient heat transfer. do not use ?thermal relief? patterns to connect the vias. it is important to have a complete connection of the plated through-hole to each plane. figure 16. pcb via pattern
isl29501 22 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8681.3 june 29, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change june 29, 2016 fn8681.3 -related literature on page 1: added ?cat shark user guide?. -pin description on page 3: updated pins 4 and 5 from "tie to dvcc or dvss" to "pull to dvcc or dvss". -ordering information table on page 4 as follows: added "isl29501-cs-evkit1z- cat shark evaluati on board" and part number isl29501irz-t7a. renamed "ISL29501-ST-EV1Z" from "evaluation board" to "sand tiger evaluation board". -principles of operation on page 8: reworded the entire section. -updated functional overview on page 9. -updated interrupt controller on page 14: removed all the subsections excluding noise rejection, which was updated as well. -updated register map table on page 17. march 8, 2016 fn8681.2 ?electrical specifications? on page 5: changed i s-hs sleep current from 1.5a to 2.5a. ?electrical specifications? on page 5: removed min and max values for vpdp and vpdn. october 7, 2015 fn8681.1 page 17: corrected and ad ded bit definitions for registers 0x01 and 0x02. page 20: moved output registers to their corre ct numerical order in the register space. page 17: corrected the bit definitions for register 0x97. page 17: added registers 0x19, 0xb0, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7. page 9: reworked i2c descriptions in the functional overview. page 15: corrected i2c timing diagrams, former figure 16 was deleted. page 17: reworded and added significant content to the cr osstalk and distance cal descriptions in calibration section. removed all references to collision detection on page12. july 1, 2015 fn8681.0 initial release
isl29501 23 fn8681.3 june 29, 2016 submit document feedback package outline drawing l24.4x5f 24 lead quad flat no-lead plastic package rev 0, 5/14 bottom view detail "x" typical recommended land pattern top view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.20mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) are for reference only. dimensioning and tolerancing conform to asmey14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 3.80 typ side view pin 1 index area 6 4.00 5.00 a 0.10 4x b 3.60 4.80 typ (20x0.50) (24x0.60) 2.60 (24x0.25) 3.60 see detail x 0.10 c c 0.08 c seating plane 0.00-0.05 0.90 0.10 c 0.203 ref 0 ~ 0.05 5 0.5x4 = 2.00 ref 0.50 0.25 0.05 20 24 0.5x6 = 3.00 ref 0.50 pin #1 index area 6 6 r0.20 19 13 7 1 24x0.40 8 12 2.60

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